What the Instruction Set Architecture is centrally focused on is defining the machine instructions that our hardware can understand.

Machine instructions, or binary code, come packaged in very specific ways. If the software generates binary that doesn’t follow the rules set out by the ISA, the hardware will fail in its processing of the data.

The way instructions are formatted is different from one architecture to the next. A Complex Instruction Set Computer (CISC) and a Reduced Instruction Set Computer (RISC) will not understand the same data.

An example machine instruction might look like this:

• 10110010011101001100100111000001

One CPU might interpret this as an instruction to add together two numbers, another might think it as a request to logically skip the next instruction if the result is true. A different CPU might not be capable of handling the data at all and return an error.

One way to quickly identify what type of computer a piece of machine code belongs to is to look at the length of the instructions. Typically, RISC computers use machine code that is all the same length, while CISC instructions can range in size from quite small all the way to 15 bytes (120 bits)!

Computers are only as intelligent as the rules we use to design and program them. Like most things in life, they follow the garbage in, garbage out principle, that is why so much time and research has been spent creating robust Instruction Set Architectures.