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Learn about the implementation of an Instruction Set Architecture (ISA) and the importance that it plays in the overall hierarchy of computer design and architecture. We will discuss the layers of abstraction that exist between the modern programmer, the student, and the machines we operate on.


Instruction Set Architecture

The CPU is just a single component of the computer's hardware, other important components of hardware include Random Access Memory (RAM), buses (high-speed wires), as well as hard disks and other non-volatile memory.

#### Random Access Memory
*Random Access Memory*, or RAM, is additional high-speed memory that a computer uses to store and access information on a short-term basis. In general, a computer’s performance can be directly correlated to the amount of RAM it has available to use. RAM is considered primary volatile memory, which means it loses whatever is stored on it as soon as power is disconnected.

#### Buses
A *bus* is an engineering term for a job-specific high-speed wire. These wires are often grouped together in bundles and will transfer electrical signals either in parallel or in serial &mdash; that is, many signals at once or one pulse at a time. Buses can be grouped into three functions: data buses, address buses, and control buses.

*Data buses* carry data back and forth between the processor and other components. Data buses are bidirectional, which means that they transfer data both to and from other locations.

*Address buses* carry a specific address in memory and are unidirectional. We can visualize all of our memory like a village with each house representing a package of data. Every house/data has an address. When our computer tells a program or component what data to use, it sends the address and then the component knows where to find the data when it needs it.

*Control buses* are also unidirectional and are responsible for carrying the control signals of the CU to other components as well as the clock signals for synchronization.

#### Hard Disks

Hard disks, or hard drives, are responsible for the long-term, or secondary storage of data and programs. This is an example of non-volatile memory, meaning that it will retain its information when we shut down our computer. 


Additional Computer Hardware

The MIPS ISA is a simple instruction set that is broken up into three distinct types of instructions, all 32-bits in length:
- *R-Type* or *Register* MIPS instructions are used for most arithmetic and logic operations
- *I-Type* or *Immediate* instructions are used primarily for data transfer and immediate operations using constants
- *J-Type* or *Jump* instructions are used to jump the program to the specific instruction, such as in a loop

Along with the instruction types, it also details that each CPU will have 32 registers, each capable of holding a 32-bit piece of data. MIPS operates on data that is stored in the register or with a 16 bit ‘immediate’ piece of data. Immediate data is typically a constant that can be sent to the processor so it doesn't need to take up space in a register.

MIPS is often used in distributed/embedded technologies because of its RISC architecture and concise instruction set. Some advantages to this in a small system include limited space requirements, increased battery life, and little to no customer interaction.

##### Instruction Format

Here is a sample R-type instruction:
```
000000 00000 00000 00000 00000 000000
  op    rs    rt    rd   shamt  func
```
All R-type instructions use this instruction format according to the MIPS documentation. This example introduces several abbreviations above in the machine code/instructions. They will be used throughout the rest of this lesson,  so let’s define them now:

|Abbreviation|Definition|
|---|---|
|`op`|OPCODE|
|`rs`|first source register|
|`rt`|second source register|
|`rd`|destination register|
|`shamt`|bit shift amount|
|`func`|extra bits for additional functions|


MIPS Instructions

An *Instruction Set Architecture*, or ISA, acts as a translator between our hardware and software. ISA is the defined set of instructions that our hardware can understand and how the software can interact with it.

Once we know what purpose the ISA is serving, we can place it into the overall hierarchy of the computer architecture. We can think of our computer system as a well-organized hamburger such as the picture on the right:

- Our top bun is the programs we interact with every day such as the web browser you are taking this class in right now.

- These programs are written in languages like Java or Python, the next layer.

- The compiler takes these languages and with the help of assembly language, translates that code into binary.

- Binary code, also known as machine code, conforms to the Instruction Set Architecture.

- The bottom bun is the actual hardware of the computer, the CPU, memory, and other components, that will manipulate data based on the machine code we give it.

Unlike the other parts of our hamburger, the ISA is an abstract concept, and this can make it difficult to understand. The ISA is the agreement between the software and the hardware so that when we put in a specific sequence of binary data, the hardware will do a specific sequence of processing.

Before we can develop a good understanding of an Instruction Set Architecture, we’re going to review some of the hardware components we’ve already learned about.

Introduction to ISA

In the previous exercise, we created the following OPCODE example:

```
000001 01001 10111 0001101001010110
```

We now know that the first part of the bit sequence is the OPCODE, but what about the rest? The rest of the message is the operands, memory locations, and additional functions that the processor will perform.

We'll take the simple multiplication of `5 * 6` to visualize two different ISA styles, CISC and RISC, before we start to decipher the code beyond the OPCODE.

CISC machine code is so long because the goal of CISC is to reduce the total number of instructions that are fed into the hardware. It may take multiple cycles of hardware to process the instruction, but it will still get done. The original purpose was to reduce the required memory for a program because memory was very expensive and consumed lots of space:
```
Machine Code: 001010010001001010100101010100101000101010101001111010010010010100101010001010010100010100001101000111101101011010101011101001
Readable Code: MUL 5 * 6
```

RISC on the other hand, would take a CISC instruction and break it up into several very simple tasks that each require one cycle to complete. This may require more operations, but allows for multiple sequencing, or pipelining, of tasks to make up for it. Essentially, since all tasks take the same amount of time to complete, they can be executed more efficiently like so:
```
Machine Code: 00101001101001001001000100011100
Readable Code: LOAD 5 from REG 1

Machine Code: 00101001101001111001000100011100
Readable Code: LOAD 6 from REG 2

Machine Code: 00011000101001010101111000110001
Readable Code: MUL 5 * 6

Machine Code: 00111001101010100000111101010011
Readable Code: STORE 30 in REG 3
```

As we begin breaking up the remaining bits in our machine code, we will use a specific type of RISC instruction architecture called MIPS, or *Microprocessor without Interlocked Pipeline Stages*. It has a fixed 32-bit instruction length, limited instructions, and is used by most post-secondary educators for its ease of understanding. Here is a [link to the documentation](https://www.mips.com/products/architectures/mips32-2/) if you want to learn more about the MIPS architecture.

Instruction Formatting

The Instruction Set Architecture defines how hardware processes binary data. Each `0` or `1` of binary data is called a *bit* and groups of these bits are put together in specific lengths that create instructions.

While the length of a specific binary instruction varies widely based on the ISA that is being used, the first few bits are always the *OPCODE* or OPeration CODE. This sequence of bits tells the processor what type of instruction it is receiving.

Every function or calculation that a processor can perform is defined by a specific OPCODE and the CU routes the remaining bits of information to the corresponding hardware that will execute the operation. 

The list of all of these is included with the ISA documentation in the form of an OPCODE Table:

| Mnemonic | OPCODE | Layman's Definition | Formal Definition                                           |
| --- | --- | --- | --- |
| ADD | 000001 | Loads two numbers from registers and<br>saves result into another register | rs_reg <- op_reg_1 + op_reg_2       |
| LOAD | 000010 | Loads a number from a memory address <br> location into a register | rs_reg <- mem[op_reg_1_addr]      |
| STORE | 000011 | Copies data in a register to a<br>memory address for long-term storage | mem[op_reg_1_addr] <- op_reg_2 |

<br>
After the OPCODE, the remaining bits in the instruction are normally referred to as the “operands”. These are the pieces of data, sometimes presented as memory addresses or sometimes given directly as literals, on which the processor will operate.

The CPU will fetch the data from memory or registers, perform the function, and then return the result to the directed memory address or register. 

Let’s take a look at this example 32-bit instruction and identify the OPCODE:

```py
000001 01001 10111 0001101001010110
OPCODE
```

If we use the table we had from above, the first six digits are the OPCODE (`000001`), telling the CPU that this is an `ADD` function. The remaining bits provide the CPU with instruction specifics that we will cover in the next exercise.

We will be using a Python interface to process our mock instructions for the rest of this lesson, a basic OPCODE interpreter is written in the code editor.


OPCODEs

What the Instruction Set Architecture is centrally focused on is defining the machine instructions that our hardware can understand.

Machine instructions, or binary code, come packaged in very specific ways. If the software generates binary that doesn't follow the rules set out by the ISA, the hardware will fail in its processing of the data.

The way instructions are formatted is different from one architecture to the next. A _Complex Instruction Set Computer_ (CISC) and a _Reduced Instruction Set Computer_ (RISC) will not understand the same data.

An example machine instruction might look like this:
* `10110010011101001100100111000001`

One CPU might interpret this as an instruction to add together two numbers, another might think it as a request to logically skip the next instruction if the result is true. A different CPU might not be capable of handling the data at all and return an error.

One way to quickly identify what type of computer a piece of machine code belongs to is to look at the length of the instructions. Typically, RISC computers use machine code that is all the same length, while CISC instructions can range in size from quite small all the way to 15 bytes (120 bits)!

Computers are only as intelligent as the rules we use to design and program them. Like most things in life, they follow the garbage in, garbage out principle, that is why so much time and research has been spent creating robust Instruction Set Architectures.

Machine Instructions

A Central Processing Unit (CPU) is the electronic circuitry that executes instructions based on an input of binary data (0’s and 1’s).

The CPU consists of three main components:
- Control Unit (CU)
- Arithmetic and Logic Unit (ALU)
- Registers (Immediate Access Store)

The *Control Unit (CU)* is the overseer of the CPU, responsible for controlling and monitoring the input and output of data from the computer’s hardware.

The *Arithmetic and Logic Unit (ALU)* is where all the processing on your computer takes place. Even as you scroll this text box, the ALU is calculating pixel changes on the screen and sending that output to the monitor.

The *register*, or immediate access store, is limited space, high-speed memory that the CPU can use for quick processing.

These components are all wired in very specific ways in order to process data. It is important here to remember that data, to our hardware, is a series of binary, on and off, electrical pulses. These pulses are run through different wires, semiconductors, and components as a means to process and return data that is usable by the software.

The list of instructions that a CPU can support, the way the electrical pulses are sent, is what makes the foundation of the Instruction Set Architecture.


Central Procesing Unit

Congratulations on making it through the lesson on Instruction Set Architecture. We have covered a lot of ground so far so let’s review some of the key concepts:

- The Instruction Set Architecture is the set of rules that define the communication of the software and the hardware.
- Computer hardware requires instructions that are presented in a specific way every time.
- The CPU is composed of three primary components:
   - Control Unit
   - Arithmetic and Logic Unit
   - Registers
- Two primary ISA designs have emerged in the computing world, CISC and RISC, each with its own advantages and disadvantages.
- ISAs are specific to each computer. An x86 Intel CISC machine cannot run the code that was produced for an ARM RISC machine.
- Working with computers at the binary, or machine code level requires extremely precise inputs, with the help of the ISA, compilers and higher-level programming languages abstract away much of the tedious work.

In our upcoming project, we will build on the knowledge of MIPS-specific instructions we learned here to replicate a simple calculator circuit in our hardware. We will create four basic arithmetic functions that will simulate the inputs and outputs of the Arithmetic and Logic Unit (ALU).

Conclusion

Now that we have a general understanding of the CPU, let's dive a little deeper.

#### Control Unit

The Control Unit is the component receiving instructions from the software and running the show. Its primary job is making sure that data is sent to the right component, at the right time, and arrives with integrity. 

Part of this job is keeping all the hardware working on the same schedule. It does this with a clock, which sends out a regular electrical signal to all components at the same time to coordinate activities.

#### ALU

The ALU is the fundamental building block of the CPU, the brains of the entire computer. Nearly all functional processing occurs in this chip. As the name implies, the ALU’s functions can be divided into two primary areas:
- Arithmetic operations that deal with calculating data (e.g. `5 * 4 = 20`)
- Logic operations that deal with comparisons and conditionals (e.g. `25 > 10`)

#### Registers

Registers are small pieces of memory right on the CPU. They are fixed in number and defined in the Instruction Set Architecture. There are typically 8, 16, 32, or 64 registers depending on the architecture and are also fixed in size based on the size of the number it can hold. They provide the CPU with a place to store and access values that are crucial to the immediate calculations the ALU is processing.

CPUs Continued

R-Type instructions are the most common in MIPS and give us a good way of understanding how an ISA defines the process that a CPU goes through when receiving data.

All R-type instructions have an `op` of ‘000000’ which signifies to the processor to look at the `func` bits to determine which process to execute.

The three references to registers, (`rs`, `rt`, `rd`) directly call them by number. There are 32 registers in a MIPS system and the five bits will produce 32 numbers (0 as `00000` to 31 as `11111`). The first two (`rs` & `rt`) are the operands and the last (`rd) is where to store the result.

The shift amount is used to shift the number by the amount in the shift bits, for our purposes this will always be `00000`, meaning no shift. The last six bits are the function to be performed on the operands.

Let’s take a look at this example instruction:

```
000000 00101 10010 00110 00000 100000
  op    rs    rt    rd   shamt  func
```
Now, let's break the instruction down:
* op -> `000000` signifies an R-Type instruction
* rs -> `00101` gets contents in Register 5
* rt -> `10010` gets contents in Register 18
* rd -> `00110` sets the result in Register 6
* shamt -> `00000` means there is no shift
* func -> `100000` function signature for adding


Our processor will add the contents of Register 5 (`16`) and Register 18 (`103`) and store that result (`119`) into Register 6. In the example, these numbers are shown as integers, but in the registers they will be stored in binary. Notice that the first register is always `0` and is a protected register, this is common in most ISAs.