Pipelining is a processing technique that efficiently maximizes the throughput of multiple computer instructions by processing the instructions in overlapping phases.
Let’s reexamine the instruction processing cycle:
- Fetch Instruction
- Decode Instruction
- Memory Access
- Registry Write Back
Earlier in this lesson, we talked about how a processor could go through these one at a time for each instruction before starting to process the next. Systems do not do this; instead, they pipeline the instructions much like our laundry example.
When instruction 1 finishes the fetch stage and moves onto the decode step, the CPU starts the fetch stage with instruction 2. In the third cycle, when instruction 1 is on the execute stage and instruction 2 is on the decode stage, instruction 3 is in the fetch stage.
If four instructions were to be processed with pipelining, it would complete in 8 cycles - a significant difference over our original 20.
Take a look at the image to the right to see a visualization of pipelining instructions. An instruction will not move on to the next phase of the processing cycle until the preceding instruction finishes that phase.
Compare this pipelined example to the linear example earlier in the lesson. Notice the improvement to total throughput with no change to the individual instruction.