In order for a single instruction to be executed by the CPU, it must go through the instruction cycle (also sometimes referred to as the fetch-execute cycle). While this cycle can vary from CPU to CPU, they typically consist of the following stages:
Instruction pipelining is a hardware-based technique in which the processor attempts to improve the throughput of a group of instructions by simultaneously processing as many instructions as effectively possible.
In instruction pipelining, an increase in the number of steps in a pipeline causes the following side effects:
In instruction parallelism, there are three types of hazards: Structural, Data, and Control.
There is no way to remove all hazards from a pipeline - manufacturers can only reduce the risk/impact.
Structural hazards are a limitation of the hardware itself. Structural hazards occur when there are not enough resources to execute multiple instructions.
Data hazards occur when an instruction is dependent on another instruction still in the pipeline.
Control hazards occur when the system doesn’t know which set of instructions will need to be processed. This occurs with branches, loops, or conditional statements.
Processors that take advantage of superscalar methodology are designed to use a methodology of parallelism where instructions are sent to different execution units at the same time, allowing for more than one instruction to be processed in a single clock cycle. In a superscalar processor, each execution unit (such as an ALU) is within a single CPU.
Instruction Parallelism processing has limitations that put a restriction on the number of simultaneous processes that are possible. These include: